An integrated circuit (IC) layout specifies portions of various components of an IC. When the IC is to include a large number of registers, latches, flip-flops and/or other types of clocked devices (“sinks”) that are to be clocked by one or more clocks, the IC must include one or more clock trees for delivering the clock signal from the clock source to all of the sinks to be clocked by it. A clock tree distributes a clock signal from its root to a set of sinks within an IC through a branching network of fan-out drivers (e.g., buffers or inverters). A single driver distributes the clock signal to a grouping of sinks referred to as a “clock net.”
Electronic design automation (EDA) software systems commonly perform clock-tree construction. As part of clock-tree construction, the EDA software assigns a position to each net driver so that a possible tree topology can be evaluated. While this initial position may be later refined by the EDA software, the position assignments determined during clock-tree construction determine an overall tree topology thereby impacting the performance of the IC device. According to one conventional approach, a minimum bounding box is determined for all sinks in a clock net, and a net driver is placed at the center of the bounding box. Although this approach can provide benefits in terms of skew and electro-migration (EM), it often results in layouts with excessive wire length.